1. Field of the Invention
The present invention relates to a PWM (Pulse Width Modulation) signal generating circuit, and a power supply apparatus comprising such a PWM signal generating circuit.
2. Background Art
In control of power supply apparatus, PWM (Pulse Width Modulation) signal has been conventionally used for adjustment of output power. In recent years, from the requirements of miniaturization, realization of high performance and realization of highly enhanced function of the apparatus, realization of digital control of power supply apparatuses is being developed in place of analog control systems which have been used from the old time.
In the digital control power supply apparatuses, there is conventionally used a method of generating a PWM signal by using a counter and a comparison circuit. Specifically, e.g., a clock signal is inputted to a counter to allow the counter to perform count-up operation to input this count value and a threshold value to a comparison circuit to compare them to thereby generate a PWM signal. When count value of the counter reaches a reset value which is set to a value greater than the threshold value, the counter is reset. By changing the threshold value, duty (logic “H” time ratio) of PWM signal is changed. By changing the reset value, the period of the PWM signal is changed.
However, with this method, even if the threshold value is changed by 1 (one) for the purpose of finely changing the duty, the logic “H” time of PWM signal is only changed by one clock period. Accordingly, since change of duty becomes large, it is impossible to finely control an output power of a power supply apparatus. As a result, it is impossible to prepare a high performance power supply apparatus. On the other hand, if a clock signal having a high frequency is utilized, it is possible to finely change duty. However, utilization of a clock signal having high frequency constitutes causes to increase the cost and to increase the power consumption of the power supply apparatus.
To solve such a problem, e.g., JP Patent Publication (Kokai) No. 2005-354854 A provides a duty control method for PWM signal in which change of duty is reduced without increasing clock frequency. Since the duty is changed by changing period of the PWM signal, it can be said that this control method is a control method of realizing a change of duty to finer degree as compared to the prior art (of improving resolution of PWM signal).
Moreover, JP Patent Publication (Kokai) No. 2004-32732 A discloses a PWM control circuit in which there is used a delay circuit for performing delay by time period which is only one half of clock period by utilizing a falling signal of clock to thereby realize change of logic “H” time of PWM signal by ½ clock period to improve resolution of PWM signal.